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1. general description the lpc2109/2119/2129 are based on a 16 /32-bit arm7tdmi-s cpu with real-time emulation and embedded trace support, together with 64/128/256 kb of embedded high-speed flash memory. a 128-bit wide memo ry interface and a unique accelerator architecture enable 32-bit code execution at maximum clock rate. for critical code size applications, the alternative 16-bit thumb mode reduces code by more than 30 % with minimal performance penalty. with their compact 64-pin package, low po wer consumption, various 32-bit timers, 4-channel 10-bit adc, two advanced can channels, pwm channels and 46 fast gpio lines with up to nine external interrupt pins these microcontrollers are particularly suitable for automotive and industrial control app lications, as well as medical systems and fault-tolerant maintenance buses. with a wide range of additional serial communications interfaces, they are also suited for communi cation gateways and protocol converters as well as many other general-purpose applications. remark: throughout the data sheet, the term lpc2109/2119/2 129 will apply to devices with and without th e /00 or /01 suffixes. the /00 or the /01 suffix will be used to differentiate from other devices only when necessary. 2. features and benefits 2.1 key features brought by lpc2109/2119/2129/01 devices ? fast gpio ports enable port pin toggling up to 3.5 times faster than the original device. they also allow for a port pin to be read at any time regardless of its function. ? dedicated result registers for adc(s) reduce interrupt overhead. the adc pads are 5 v tolerant when configured for digital i/o function(s). ? uart0/1 include fractional baud rate generat or, auto-bauding capabilities and handshake flow-control fully implemented in hardware. ? buffered ssp serial controlle r supporting spi, 4-wire ssi, and microwire formats. ? spi programmable data length and master mode enhancement. ? diversified code read protection (crp) e nables different security levels to be implemented. this feature is available in lpc2109/2119/2129/00 devices as well. ? general purpose timers can operate as external event counters. 2.2 key features co mmon for all devices ? 16/32-bit arm7tdmi-s microcontroller in a tiny lqfp64 package. ? 8/16 kb on-chip sram. lpc2109/2119/2129 single-chip 16/32-bit microcontro llers; 64/128/256 kb isp/iap flash with 10-bit adc and can rev. 7 ? 14 june 2011 product data sheet
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 2 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers ? 64/128/256 kb on-chip flash program memory. 128-bit wide interface/accelerator enables high speed 60 mhz operation. ? in-system programming (isp) and in-application programming (iap) via on-chip bootloader software. flash programming takes 1 ms per 512 b line. single sector or full chip erase takes 400 ms. ? embeddedice-rt interface enables breakpoints and watch points. interrupt service routines can continue to execute while the foreground task is debugged with the on-chip realmonitor software. ? embedded trace macrocell (etm) enables non-intrusive high speed real-time tracing of instruction execution. ? two interconnected can interfaces (one for lpc2109) with advanced acceptance filters. ? four-channel 10-bit a/d converter wit h conversion time as low as 2.44 ? s. ? multiple serial interfaces incl uding two uarts (16c550), fast i 2 c-bus (400 kbit/s) and two spis. ? 60 mhz maximum cpu clock available fr om programmable on-chip phase-locked loop with settling time of 100 ? s. ? vectored interrupt controller with configur able priorities and vector addresses. ? two 32-bit timers (with four capture and four compare channels), pwm unit (six outputs), real-time clock (rtc) and watchdog. ? up to forty-six 5 v tolerant general purpose i/o pins. up to nine edge or level sensitive external interrupt pins available. ? on-chip crystal oscillator with an op erating range of 1 mhz to 30 mhz. ? two low power modes, idle and power-down. ? processor wake-up from power-down mode via external interrupt. ? individual enable/disable of periphe ral functions for power optimization. ? dual power supply: ? cpu operating voltage range of 1.65 v to 1.95 v (1.8 v ? 0.15 v). ? i/o power supply range of 3.0 v to 3.6 v (3.3 v ? 10 %) with 5 v tolerant i/o pads. 3. ordering information table 1. ordering information type number package name description version lpc2109fbd64/01 lqfp64 plastic low prof ile quad flat package; 64 leads; body 10 ? 10 ? 1.4 mm sot314-2 LPC2119FBD64/01 lqfp64 plastic low profile quad flat package; 64 leads; body 10 ? 10 ? 1.4 mm sot314-2 lpc2129fbd64/01 lqfp64 plastic low prof ile quad flat package; 64 leads; body 10 ? 10 ? 1.4 mm sot314-2
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 3 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers 3.1 ordering options table 2. ordering options type number flash memory ram can fast gpio/ ssp/ enhanced uart, adc, timer temperature range lpc2109fbd64/01 64 kb 8 kb 1 channel yes ? 40 ? c to +85 ?c LPC2119FBD64/01 128 kb 16 kb 2 channels yes ? 40 ? c to +85 ?c lpc2129fbd64/01 256 kb 16 kb 2 channels yes ? 40 ? c to +85 ?c
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 4 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers 4. block diagram (1) shared with gpio. (2) when test/debug interface is used, gpio/other functions sharing these pins are not available. (3) only 1 for lpc2109. (4) ssp interface and high-speed gpio are avail able on lpc2109/01, lpc2119/01, and lpc2129/01 only. fig 1. block diagram scl (1) p0[30:27], p0[25:0] trst (2) tms (2) tck (2) tdi (2) tdo (2) xtal2 xtal1 sck0 (1) mosi0 (1) miso0 (1) eint[3:0] (1) ain[3:0] (1) ssel0 (1) rxd[1:0] (1) ahb bridge pll pwm0 arm7tdmi-s lpc2109 lpc2119 lpc2129 reset 4 cap0 (1) 4 cap1 (1) 4 mat0 (1) td[2:1] (1) rd[2:1] (1) 4 mat1 (1) p1[31:16] p0[30:27], p0[25:0] p1[31:16] sda (1) txd[1:0] (1) dsr1 (1) , cts1 (1) , rts1 (1) , dtr1 (1) , dcd1 (1) , ri1 (1) rtck arm7 local bus internal sram controller internal flash controller 8/16 kb sram 64/128/256 kb flash external interrupts capture/ compare timer 0/timer 1 a/d converter general purpose i/o can interface 1 and 2 acceptance filters (3) test/debug interface emulation trace module amba advanced high-performance bus (ahb) system clock system functions vectored interrupt controller ahb decoder i 2 c-bus serial interface ahb to apb bridge apb divider spi0 serial interface sck1 (1) mosi1 (1) miso1 (1) ssel1 (1) spi1/ssp (4) serial interface uart0/uart1 watchdog timer system control real-time clock 002aad172 v dd(3v3) v ss v dd(1v8) pwm[6:1] (1) high-speed gpi/o (4) 46 pins total
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 5 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers 5. pinning information 5.1 pinning (1) no td2 and rd2 for lpc2109. (2) pin configuration is identical for devic es with and without /00 and /01 suffixes. fig 2. pin configuration lpc2109 lpc2119 lpc2129 (2) p0[21]/pwm5/cap1[3] p1[20]/tracesync p0[22]/cap0[0]/mat0[0] p0[17]/cap1[2]/sck1/mat1[2] p0[23]/rd2 (1) p0[16]/eint0/mat0[2]/cap0[2] p1[19]/tracepkt3 p0[15]/ri1/eint2 p0[24]/td2 (1) p1[21]/pipestat0 v ss v dd(3v3) v dda(3v3) v ss p1[18]/tracepkt2 p0[14]/dcd1/eint1 p0[25]/rd1 p1[22]/pipestat1 td1 p0[13]/dtr1/mat1[1] p0[27]/ain0/cap0[1]/mat0[1] p0[12]/dsr1/mat1[0] p1[17]/tracepkt1 p0[11]/cts1/cap1[1] p0[28]/ain1/cap0[2]/mat0[2] p1[23]/pipestat2 p0[29]/ain2/cap0[3]/mat0[3] p0[10]/rts1/cap1[0] p0[30]/ain3/eint3/cap0[0] p0[9]/rxd1/pwm6/eint3 p1[16]/tracepkt0 p0[8]/txd1/pwm4 v dd(1v8) p1[27]/tdo v ss v dda(1v8) p0[0]/txd0/pwm1 xtal1 p1[31]/trst xtal2 p0[1]/rxd0/pwm3/eint0 p1[28]/tdi p0[2]/scl/cap0[0] v ssa v dd(3v3) v ssa(pll) p1[26]/rtck reset v ss p1[29]/tck p0[3]/sda/mat0[0]/eint1 p0[20]/mat1[3]/ssel1/eint3 p0[4]/sck0/cap0[1] p0[19]/mat1[2]/mosi1/cap1[2] p1[25]/extin0 p0[18]/cap1[3]/miso1/mat1[3] p0[5]/miso0/mat0[1] p1[30]/tms p0[6]/mosi0/cap0[2] v dd(3v3) p0[7]/ssel0/pwm2/eint2 v ss p1[24]/traceclk v dd(1v8) 002aad173 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 6 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers 5.2 pin description table 3. pin description symbol pin type description p0[0] to p0[31] i/o port 0 is a 32-bit bidirectional i/ o port with individual direction controls for each bit. the operation of port 0 pins depends upon the pin function selected via the pin connect block. pins 26 and 31 of port 0 are not available. p0[0]/txd0/ pwm1 19 o txd0 ? transmitter output for uart0. o pwm1 ? pulse width modulator output 1. p0[1]/rxd0/ pwm3/eint0 21 i rxd0 ? receiver input for uart0. o pwm3 ? pulse width modulator output 3. i eint0 ? external interrupt 0 input p0[2]/scl/ cap0[0] 22 i/o scl ? i 2 c-bus clock input/output. open-drain output (for i 2 c-bus compliance). i cap0[0] ? capture input for timer 0, channel 0. p0[3]/sda/ mat0[0]/eint1 26 i/o sda ? i 2 c-bus data input/output. open-drain output (for i 2 c-bus compliance). o mat0[0] ? match output for timer 0, channel 0. i eint1 ? external interrupt 1 input. p0[4]/sck0/ cap0[1] 27 i/o sck0 ? serial clock for spi0. sp i clock output from master or input to slave. i cap0[1] ? capture input for timer 0, channel 1. p0[5]/miso0/ mat0[1] 29 i/o miso0 ? master in slave out for spi0. data input to spi master or data output from spi slave. o mat0[1] ? match output for timer 0, channel 1. p0[6]/mosi0/ cap0[2] 30 i/o mosi0 ? master out slave in for spi0. data ou tput from spi master or data input to spi slave. i cap0[2] ? capture input for timer 0, channel 2. p0[7]/ssel0/ pwm2/eint2 31 i ssel0 ? slave select for spi0. selects the spi interface as a slave. o pwm2 ? pulse width modulator output 2. i eint2 ? external interrupt 2 input. p0[8]/txd1/ pwm4 33 o txd1 ? transmitter output for uart1. o pwm4 ? pulse width modulator output 4. p0[9]/rxd1/ pwm6/eint3 34 i rxd1 ? receiver input for uart1. o pwm6 ? pulse width modulator output 6. i eint3 ? external interrupt 3 input. p0[10]/rts1/ cap1[0] 35 o rts1 ? request to send output for uart1. i cap1[0] ? capture input for timer 1, channel 0. p0[11]/cts1/ cap1[1] 37 i cts1 ? clear to send input for uart1. i cap1[1] ? capture input for timer 1, channel 1. p0[12]/dsr1/ mat1[0] 38 i dsr1 ? data set ready input for uart1. o mat1[0] ? match output for timer 1, channel 0. p0[13]/dtr1/ mat1[1] 39 o dtr1 ? data terminal ready output for uart1. o mat1[1] ? match output for timer 1, channel 1. p0[14]/dcd1/ eint1 41 i dcd1 ? dat a carrier detect input for uart1. i eint1 ? external interrupt 1 input. note: low on this pin while reset is low forces on-chip bootloader to take control of the part after reset.
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 7 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers p0[15]/ri1/eint2 45 i ri1 ? ring indicator input for uart1. i eint2 ? external interrupt 2 input. p0[16]/eint0/ mat0[2]/cap0[2] 46 i eint0 ? external interrupt 0 input. o mat0[2] ? match output for timer 0, channel 2. i cap0[2] ? capture input for timer 0, channel 2. p0[17]/cap1[2]/ sck1/mat1[2] 47 i cap1[2] ? capture input for timer 1, channel 2. i/o sck1 ? serial clock for spi1/ssp [1] . spi clock output from master or input to slave. o mat1[2] ? match output for timer 1, channel 2. p0[18]/cap1[3]/ miso1/mat1[3] 53 i cap1[3] ? capture input for timer 1, channel 3. i/o miso1 ? master in slave out for spi1/ssp [1] . data input to spi master or data output from spi slave. o mat1[3] ? match output for timer 1, channel 3. p0[19]/mat1[2]/ mosi1/cap1[2] 54 o mat1[2] ? match output for timer 1, channel 2. i/o mosi1 ? master out slave in for spi1/ssp [1] . data output from spi master or data input to spi slave. i cap1[2] ? capture input for timer 1, channel 2. p0[20]/mat1[3]/ ssel1/eint3 55 o mat1[3] ? match output for timer 1, channel 3. i ssel1 ? slave select for spi1/ssp [1] . selects the spi interface as a slave. i eint3 ? external interrupt 3 input. p0[21]/pwm5/ cap1[3] 1o pwm5 ? pulse width modulator output 5. i cap1[3] ? capture input for timer 1, channel 3. p0[22]/cap0[0]/ mat0[0] 2i cap0[0] ? capture input for timer 0, channel 0. o mat0[0] ? match output for timer 0, channel 0. p0[23]/rd2 3 i can2 receiver inpu t (not available on lpc2109). p0[24]/td2 5 o can2 transmitter ou tput (not available on lpc2109). p0[25]/rd1 9 i can1 receiver input. p0[27]/ain0/ cap0[1]/mat0[1] 11 i ain0 ? a/d converter, input 0. this analog input is always connected to its pin. i cap0[1] ? capture input for timer 0, channel 1. o mat0[1] ? match output for timer 0, channel 1. p0[28]/ain1/ cap0[2]/mat0[2] 13 i ain1 ? a/d converter, input 1. this analog input is always connected to its pin. i cap0[2] ? capture input for timer 0, channel 2. o mat0[2] ? match output for timer 0, channel 2. p0[29]/ain2/ cap0[3]/mat0[3] 14 i ain2 ? a/d converter, input 2. this analog input is always connected to its pin. i cap0[3] ? capture input for timer 0, channel 3. o mat0[3] ? match output for timer 0, channel 3. p0[30]/ain3/ eint3/cap0[0] 15 i ain3 ? a/d converter, input 3. this analog input is always connected to its pin. i eint3 ? external interrupt 3 input. i cap0[0] ? capture input for timer 0, channel 0. p1[0] to p1[31] i/o port 1 is a 32-bit bidirectional i/ o port with individual direction controls for each bit. the operation of port 1 pins depends upon the pin function selected via the pin connect block. pins 0 through 15 of port 1 are not available. table 3. pin description ?continued symbol pin type description
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 8 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers p1[16]/ tracepkt0 16 o trace packet, bit 0. standard i/o port with internal pull-up. p1[17]/ tracepkt1 12 o trace packet, bit 1. standard i/o port with internal pull-up. p1[18]/ tracepkt2 8 o trace packet, bit 2. standard i/o port with internal pull-up. p1[19]/ tracepkt3 4 o trace packet, bit 3. standard i/o port with internal pull-up. p1[20]/ tracesync 48 o trace synchronization. standard i/o port with internal pull-up. note: low on this pin while reset is low, enables pins p1[25:16] to operate as trace port after reset. p1[21]/ pipestat0 44 o pipeline status, bit 0. standard i/o port with internal pull-up. p1[22]/ pipestat1 40 o pipeline status, bit 1. standard i/o port with internal pull-up. p1[23]/ pipestat2 36 o pipeline status, bit 2. standard i/o port with internal pull-up. p1[24]/ traceclk 32 o trace clock. standard i/o port with internal pull-up. p1[25]/extin0 28 i external trigger input. standard i/o with internal pull-up. p1[26]/rtck 24 i/o returned test clock output. extra signal added to the jtag port. assists debugger synchronization when processor frequency varies. bidirectional pin with internal pull-up. note: low on this pin while reset is low, enables pins p1[31:26] to operate as debug port after reset. p1[27]/tdo 64 o test data out for jtag interface. p1[28]/tdi 60 i test data in for jtag interface. p1[29]/tck 56 i test clock for jtag interf ace. this clock must be slower than 1 6 of the cpu clock (cclk) for the jtag interface to operate. p1[30]/tms 52 i test mode select for jtag interface. p1[31]/trst 20 i test reset for jtag interface. td1 10 o can1 transmitter output. reset 57 i external reset input; a low on this pin resets the device, causing i/o ports and peripherals to take on their default states, and processor execution to begin at address 0. ttl with hysteresis, 5 v tolerant. xtal1 62 i input to the oscillator circuit and internal clock generator circuits. xtal2 61 o output from the oscillator amplifier. v ss 6, 18, 25, 42, 50 i ground: 0 v reference. v ssa 59 i analog ground; 0 v reference. this should nominally be the same voltage as v ss , but should be isolated to minimize noise and error. v ssa(pll) 58 i pll analog ground; 0 v reference. this should nominally be the same voltage as v ss , but should be isolated to minimize noise and error. v dd(1v8) 17, 49 i 1.8 v core power supply; this is the power supply voltage for internal circuitry. table 3. pin description ?continued symbol pin type description
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 9 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers [1] ssp interface available on lpc2109/01, lpc2119/01, and lpc2129/01 only. v dda(1v8) 63 i analog 1.8 v core power supply; this is the power supply voltage for internal circuitry. this should be nominally the same voltage as v dd(1v8) but should be isolated to minimize noise and error. v dd(3v3) 23, 43, 51 i 3.3 v pad power supply; this is the power supply voltage for the i/o ports. v dda(3v3) 7 i analog 3.3 v pad power supply; this should be nominally the same voltage as v dd(3v3) but should be isolated to minimize noise and error. table 3. pin description ?continued symbol pin type description
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 10 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers 6. functional description details of the lpc2109/2119/2129 systems an d peripheral functions are described in the following sections. 6.1 architectural overview the arm7tdmi-s is a general purpose 32-b it microprocessor, which offers high performance and very low power consumpt ion. the arm architecture is based on reduced instruction set comput er (risc) principles, and the instruction set and related decode mechanism are much simpler than those of microprogrammed complex instruction set computers. this simplicity re sults in a high instruction throughput and impressive real-time interrupt response from a small and cost-effective processor core. pipeline techniques are employed so that all parts of the processing and memory systems can operate continuously. typically, while one instruction is being executed, its successor is being decoded, and a third instruction is being fetched from memory. the arm7tdmi-s processor also employs a unique architectural strategy known as thumb, which makes it ideally suited to high-volume applications with memory restrictions, or applications where code density is an issue. the key idea behind thumb is that of a super-reduced instruction set. essentially, the arm7tdmi-s processor has two instruction sets: ? the standard 32-bit arm set. ? a 16-bit thumb set. the thumb set?s 16-bit instru ction length allows it to approach twice the density of standard arm code while retaining most of the arm?s performance advantage over a traditional 16-bit processor using 16-bit regist ers. this is possible because thumb code operates on the same 32-bit register set as arm code. thumb code is able to provide up to 65 % of the code size of arm, and 160 % of the performance of an equivalent arm processo r connected to a 16-bit memory system. 6.2 on-chip flash program memory the lpc2109/2119/2129 incorpor ate a 64/128/256 kb flash memory system, respectively. this memory may be used for both code and data storage. programming of the flash memory may be accomplished in several ways. it may be programmed in system via the serial port. the application program may also erase and/or program the flash while the application is running, allowing a great degree of fl exibility for data storage field firmware upgrades, etc. when on-chip bootloader is used, 60/120/248 kb of flash memory is available for user code. the lpc2109/2119/2129 flash memory provides a minimum of 100000 erase/write cycles and 20 years of data retention. on-chip bootloader (as of revision 1.60) prov ides code read protection (crp) for the lpc2109/2119/2129 on-chip flash memory. when the crp is enabled, the jtag debug port and isp commands accessing either the on-chip ram or flash memory are disabled.
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 11 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers however, the isp flash erase command can be executed at any time (no matter whether the crp is on or off). removal of crp is achi eved by erasure of full on-chip user flash. with the crp off, full access to the ch ip via the jtag and/or isp is restored. 6.3 on-chip sram on-chip sram may be used for code and/or data storage. the sram may be accessed as 8 bit, 16 bit, and 32 bit. the lpc2109/2119/2129 provide 8 kb of sram for the lpc2109 and 16 kb for the lpc2119 and lpc2129. 6.4 memory map the lpc2109/2119/2129 memory maps incorporate several distinct regions, as shown in figure 3 . in addition, the cpu interrupt vectors may be re-mapped to allow them to reside in either flash memory (the default) or on-chip sram. this is described in section 6.18 ? system control ? .
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 12 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers 6.5 interrupt controller the vectored interrupt controller (vic) accepts all of the interrupt request inputs and categorizes them as fa st interrupt request (f iq), vectored interrupt request (irq), and non-vectored irq as defined by programmable settings. the programmable assignment scheme means that priorities of interrupts fr om the various peripherals can be dynamically assigned and adjusted. fiq has the highest priority. if more than one request is assigned to fiq, the vic combines the requests to produce the fiq signal to the arm processor. the fastest possible fiq latency is achieved when only on e request is classified as fiq because then the fiq service routine can simply start dea ling with that device. but if more than one request is assigned to the fiq class, the fiq service routine can read a word from the vic that identifies which fiq source(s) is (are) requesting an interrupt. fig 3. lpc2109/2119/2129 memory map ahb peripherals apb peripherals reserved address space boot block (re-mapped from on-chip flash memory) reserved address space 16 kb on-chip static ram (lpc2119/2129) 8 kb on-chip static ram (lpc2109) reserved address space 256 kb on-chip flash memory (lpc2129) 0xffff ffff 0xf000 0000 0xefff ffff 0xe000 0000 0xc000 0000 0xdfff ffff 0x8000 0000 0x7fff ffff 0x7fff e000 0x7fff dfff 0x4000 4000 0x4000 3fff 0x4000 0000 0x4000 1fff 0x3fff ffff 0x0004 0000 0x0003 ffff 0x0002 0000 0x0001 0000 4.0 gb 3.75 gb 3.5 gb 3.0 gb 2.0 gb 1.0 gb 0.0 gb 128 kb on-chip flash memory (lpc2119) 64 kb on-chip flash memory (lpc2109) 0x0001 ffff 0x0000 0000 0x0000 ffff 002aad174
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 13 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers vectored irqs have the middle priority. sixtee n of the interrupt requests can be assigned to this category. any of the interrupt requests can be assigned to any of the 16 vectored irq slots, among which slot 0 has the highest priority and slot 15 has the lowest. non-vectored irqs have the lowest priority. the vic combines the requests from all the vectored and non-vectored irqs to produce the irq signal to the arm processor. the irq service routine can start by reading a register from the vic and jumping there. if any of the vectored irqs are requesting, the vic provides the address of the highest-pr iority requesting irqs service routine, otherwise it provides the address of a default routine that is shared by all the non-vectored irqs. the default routine can read another vi c register to see what irqs are active. 6.5.1 interrupt sources ta b l e 4 lists the interrupt sources for each peripheral function. each peripheral device has one interrupt line connected to the vectored interrupt controller, but may have several internal interrupt flags. individual interrupt flags may also represent more than one interrupt source. table 4. interrupt sources block flag(s) vic channel # wdt watchdog interrupt (wdint) 0 - reserved for software interrupts only 1 arm core embeddedice, dbgcommrx 2 arm core embeddedice, dbgcommtx 3 timer 0 match 0 to 3 (mr0, mr1, mr2, mr3) capture 0 to 3 (cr0, cr1, cr2, cr3) 4 timer 1 match 0 to 3 (mr0, mr1, mr2, mr3) capture 0 to 3 (cr0, cr1, cr2, cr3) 5 uart0 rx line status (rls) transmit holding register empty (thre) rx data available (rda) character time-out indicator (cti) 6 uart1 rx line status (rls) transmit holding register empty (thre) rx data available (rda) character time-out indicator (cti) modem status interrupt (msi) 7 pwm0 match 0 to 6 (mr0, mr1, mr2, mr3, mr4, mr5, mr6) 8 i 2 c-bus si (state change) 9 spi0 spif, modf 10 spi1 and ssp [1] spif, modf and txris, rxris, rtris, rorris 11 pll pll lock (plock) 12 rtc rtccif (counter increment), rtcalf (alarm) 13
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 14 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers [1] ssp interface available on lpc2109/01, lpc2119/01, and lpc2129/01 only. 6.6 pin connect block the pin connect block allows selected pins of the microcontroller to have more than one function. configuration registers control the multiplexers to allow connection between the pin and the on-chip peripherals. peripherals s hould be connected to the appropriate pins prior to being activated, and prior to any related interrupt(s) being enabled. activity of any enabled peripheral function that is not ma pped to a related pin should be considered undefined. 6.7 general purpose parallel i/o (gpio) and fast i/o device pins that are not connec ted to a specific peripheral function are controlled by the parallel i/o registers. pins may be dynamically configured as inputs or outputs. separate registers allow setting or clearing any number of outputs simultaneously. the value of the output register may be read back, as we ll as the current state of the port pins. 6.7.1 features ? bit-level set and clear registers allow a single instruction set or clear of any number of bits in one port. ? direction control of individual bits. ? separate control of output set and clear. ? all i/o default to inputs after reset. 6.7.2 features added with the fast gpio set of registers available on lpc2109/2119/2129/01 only ? fast gpio registers are relocated to the arm local bus for the fastest possible i/o timing, enabling port pin toggling up to 3.5 times faster than earlier lpc2000 devices. ? mask registers allow treating sets of por t bits as a group, leaving other bits unchanged. ? all fast gpio registers are byte addressable. ? entire port value can be written in one instruction. ? ports are accessible via either the legacy group of registers (gpios) or the group of registers providing accelerated port access (fast gpios). system control external interrupt 0 (eint0) 14 external interrupt 1 (eint1) 15 external interrupt 2 (eint2) 16 external interrupt 3 (eint3) 17 adc a/d converter 18 can can1, can2 and acceptance filter 19 to 23 table 4. interrupt sources ?continued block flag(s) vic channel #
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 15 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers 6.8 10-bit adc the lpc2109/2119/2129 each contain a single 10-bit successive approximation adc with four multiplexed channels. 6.8.1 features ? measurement range of 0 v to 3 v. ? capable of performing more than 400000 10-bit samples per second. ? burst conversion mode for single or multiple inputs. ? optional conversion on transition on input pin or timer match signal. 6.8.2 adc features available in lpc2109/2119/2129/01 only ? every analog input has a dedicated result register to reduce interrupt overhead. ? every analog input can generate an interrupt once the conversion is completed. ? the adc pads are 5 v tolerant when configured for digital i/o function(s). 6.9 can controllers and acceptance filter the lpc2119 and lpc2129 each contain two can controllers, while the lpc2109 has one can controller. the can is a serial communications protocol which efficiently supports distributed real-time control with a very high level of security. its domain of application ranges from high-speed ne tworks to low-cost multiplex wiring. 6.9.1 features ? data rates up to 1 mbit/s on each bus. ? 32-bit register and ram access. ? compatible with can specification 2.0 b, iso 11898-1. ? global acceptance filter recognizes 11-bit an d 29-bit rx identifi ers for all can buses. ? acceptance filter can provide fullcan-s tyle automatic reception for selected standard identifiers. 6.10 uarts the lpc2109/2119/2129 each contain two uart s. in addition to standard transmit and receive data lines, the uart1 also provides a full modem control handshake interface. 6.10.1 features ? 16 b receive and transmit fifos. ? register locations conform to 16c550 industry standard. ? receiver fifo trigger points at 1 b, 4 b, 8 b, and 14 b. ? built-in fractional baud rate generator cove ring wide range of baud rates without a need for external crystals of particular values. ? transmission fifo control enables implem entation of software (xon/xoff) flow control on both uarts.
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 16 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers ? uart1 is equipped with standard modem interface signals. this module also provides full support for hardware flow control (auto-cts/rts). 6.10.2 uart features available in lpc2109/2119/2129/01 only compared to previous lpc2000 microcontrollers, uarts in lpc2109/2119/2129/01 introduce a fractional baud rate generator for both uarts, enabling these microcontrollers to achieve standard baud rates such as 115200 bd with any crystal frequency above 2 mhz. in addition, auto-cts/rts flow-control functions are fully implemented in hardware. ? fractional baud rate generator enables standard baud rates such as 115200 bd to be achieved with any crystal frequency above 2 mhz. ? auto-bauding. ? auto-cts/rts flow-control fu lly implemented in hardware. 6.11 i 2 c-bus serial i/o controller the i 2 c-bus is a bidirectional bus for inter-ic co ntrol using only two wires: a serial clock line (scl), and a serial data line (sda). each device is recognized by a unique address and can operate as either a receiver-only device (e.g. an lcd driver or a transmitter with the capability to both receive and send information (such as memory). transmitters and/or receivers can operate in either master or sl ave mode, depending on whether the chip has to initiate a data transfer or is only addressed. the i 2 c-bus is a multi-mast er bus; it can be controlled by more than one bus master connected to it. the i 2 c-bus implemented in lpc2109/2119/2129 supports a bit rate up to 400 kbit/s (fast i 2 c-bus). 6.11.1 features ? standard i 2 c-bus compliant interface. ? easy to configure as master, slave, or master/slave. ? programmable clocks allow versatile rate control. ? bidirectional data transfer between masters and slaves. ? multi-master bus (no central master). ? arbitration between simultaneously transmit ting masters without corruption of serial data on the bus. ? serial clock synchronization allows devices with different bit rates to communicate via one serial bus. ? serial clock synchronization can be used as a handshake mechanism to suspend and resume serial transfer. ? the i 2 c-bus may be used for test and diagnostic purposes.
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 17 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers 6.12 spi serial i/o controller the lpc2109/2119/2129 each contain two spis. the spi is a full duplex serial interface, designed to be able to handle multiple masters and slaves connected to a given bus. only a single master and a single slave can communicate on the interface during a given data transfer. during a data transfer the master a lways sends a byte of data to the slave, and the slave always sends a byte of data to the master. 6.12.1 features ? compliant with serial peripheral interface (spi) specification. ? synchronous, serial, full duplex communication. ? combined spi master and slave. ? maximum data bit rate of 1 8 of the input clock rate. 6.12.2 features available in lpc2109/2119/2129/01 only ? eight to 16 bits per frame. ? when the spi interface is used in master mode, the sseln pin is not needed (can be used for a different function). 6.13 ssp controller (lpc2109/2119/2129/01 only) remark: this peripheral is available in lpc2109/2119/2129/01 only. the ssp is a controller capable of operation on a spi , 4-wire ssi, or micr owire bus. it can interact with multiple masters and slaves on the bus. only a single master and a single slave can communicate on the bus during a given data transfer. data transfers are in principle full duplex, with frames of four to 16 bits of data flowing from the master to the slave and from the slave to the master. while the ssp and spi1 peripherals share the same physical pins, it is not possible to have both of these two peripherals active at the same time. application can switch on the fly from spi1 to ssp and back. 6.13.1 features ? compatible with motorola?s spi, texas instrument?s 4-wire ssi, and national semiconductor?s microwire buses. ? synchronous serial communication. ? master or slave operation. ? 8-frame fifos for both transmit and receive. ? four to 16 bits per frame. 6.14 general purpose timers the timer/counter is designed to count cycles of the peripheral clock (pclk) or an externally supplied clock and optionally generate interrupts or perform other actions at specified timer values, based on four match regi sters. it also includes four capture inputs
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 18 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers to trap the timer value when an input signal transitions, optionally generating an interrupt. multiple pins can be selected to perform a si ngle capture or match function, providing an application with ?or? and ?and?, as well as ?broadcast? functions among them. 6.14.1 features ? a 32-bit timer/counter with a programmable 32-bit prescaler. ? timer or external event counter operation ? four 32-bit capture channels per timer that can take a snapshot of the timer value when an input signal transitions. a capture event may also optionally generate an interrupt. ? four 32-bit match registers that allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? four external outputs per timer correspondi ng to match registers, with the following capabilities: ? set low on match. ? set high on match. ? toggle on match. ? do nothing on match. 6.14.2 features available in lpc2109/2119/2129/01 only the lpc2109/2119/2129/01 can count external events on one of the capture inputs if the external pulse lasts at least one half of the period of the pclk. in this configuration, unused capture lines can be selected as regular timer capture inputs, or used as external interrupts. ? timer can count cycles of either the perip heral clock (pclk) or an externally supplied clock. ? when counting cycles of an externally supp lied clock, only one of the timer?s capture inputs can be selected as the timer?s clock. the rate of such a clock is limited to pclk / 4. duration of high/low levels on the selected capn input cannot be shorter than 1 / (2pclk). 6.15 watchdog timer the purpose of the watchdog is to reset the mi crocontroller within a reasonable amount of time if it enters an erroneous state. when enabl ed, the watchdog w ill generate a system reset if the user program fails to ?feed? (o r reload) the watchdog within a predetermined amount of time. 6.15.1 features ? internally resets chip if not period ically reloaded. ? debug mode.
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 19 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers ? enabled by software but requires a hardware reset or a watchdog reset/interrupt to be disabled. ? incorrect/incomplete feed sequence c auses reset/interrupt if enabled. ? flag to indicate watchdog reset. ? programmable 32-bit timer with internal pre-scaler. ? selectable time period from (t cy(pclk) ? 256 ? 4) to (t cy(pclk) ? 2 32 ? 4) in multiples of t cy(pclk) ? 4. 6.16 real-time clock the rtc is designed to provide a set of coun ters to measure time when normal or idle operating mode is selected. the rtc has be en designed to use little power, making it suitable for battery powered systems where the cpu is not running continuously (idle mode). 6.16.1 features ? measures the passage of time to maintain a calendar and clock. ? ultra low power design to support battery powered systems. ? provides seconds, minutes, hours, day of month, month, year, day of week, and day of year. ? programmable reference clock divider allows adjustment of the rtc to match various crystal frequencies. 6.17 pulse width modulator the pwm is based on the standard timer block and inherits all of its features, although only the pwm function is pinned out on the lpc2109/2119/2129. the timer is designed to count cycles of the peripheral cl ock (pclk) and optionally ge nerate interrupt s or perform other actions when specified timer values o ccur, based on seven match registers. the pwm function is also based on match register events. the ability to separately contro l rising and falling edge locations allo ws the pwm to be used for more applications. for instance, mu lti-phase motor control typically requires three non-overlapping pwm outputs with individual control of all three pulse widths and positions. two match registers can be used to provide a single edge controlled pwm output. one match register (mr0) controls the pwm cycl e rate, by resetting t he count upon match. the other match register controls the pw m edge position. additional single edge controlled pwm outputs require only one match re gister each, since the repetition rate is the same for all pwm outputs. multiple single edge contro lled pwm outputs will all have a rising edge at the beginning of each pwm cycle, when an mr0 match occurs.
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 20 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers three match registers can be used to provid e a pwm output with both edges controlled. again, the mr0 match register controls th e pwm cycle rate. the other match registers control the two pwm edge positions. additi onal double edge controlled pwm outputs require only two match registers each, since the repetition rate is the same for all pwm outputs. with double edge controlled pwm outputs, spec ific match registers control the rising and falling edge of the output. this allows both positive going pwm pulses (when the rising edge occurs prior to the falling edge), and negative goi ng pwm pulses (when the falling edge occurs prior to the rising edge). 6.17.1 features ? seven match registers allow up to six single edge controlled or three double edge controlled pwm outputs, or a mix of both types. ? the match registers also allow: ? continuous operation with optional interrupt generation on match. ? stop timer on match with optional interrupt generation. ? reset timer on match with optional interrupt generation. ? supports single edge controlled and/or double edge controlled pwm outputs. single edge controlled pwm outputs all go high at the beginning of each cycle unless the output is a constant low. double edge co ntrolled pwm outputs can have either edge occur at any position within a cycle. this a llows for both positive going and negative going pulses. ? pulse period and width can be any number of timer counts. this allows complete flexibility in the trad e-off between resolution and re petition rate. all pwm outputs will occur at the same repetition rate. ? double edge controlled pwm outputs can be programmed to be either positive going or negative going pulses. ? match register updates are synchronized wit h pulse outputs to prevent generation of erroneous pulses. software must ?release? new match values before they can become effective. ? may be used as a standard timer if the pwm mode is not enabled. ? a 32-bit timer/counter with a programmable 32-bit prescaler. 6.18 system control 6.18.1 crystal oscillator the oscillator supports crysta ls in the range of 1 mhz to 30 mhz. the oscillator output frequency is called f osc and the arm processor clock frequen cy is referred to as cclk for purposes of rate equations, etc.. f osc and cclk are the same value unless the pll is running and connected. refer to section 6.18.2 ? pll ? for additional information.
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 21 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers 6.18.2 pll the pll accepts an input clock frequency in the range of 10 mhz to 25 mhz. the input frequency is multiplied up into the range of 10 mhz to 60 mhz with a current controlled oscillator (cco). the mu ltiplier can be an integer value from 1 to 32 (in practice, the multiplier value cannot be higher than 6 on this family of microcontrollers due to the upper frequency limit of the cpu). the cco operates in the range of 156 mhz to 320 mhz, so there is an additional divider in the loop to keep the cco within its frequency range while the pll is providing the desired output frequenc y. the output divider may be set to divide by 2, 4, 8, or 16 to produce the output clock. since the minimum output divider value is 2, it is insured that the pll output has a 50 % duty cycle. the pll is turned off and bypassed following a chip reset and may be enabled by software. the program must configure and activate the pll, wait for the pll to lock, then connect to the pll as a clock source. the pll settling time is 100 ? s. 6.18.3 reset and wake-up timer reset has two sources on the lpc2109/2119/2129: the reset pin and watchdog reset. the reset pin is a schmitt trigger input pin with an additional glitch filter. assertion of chip reset by any source starts the wake-up timer (see wake-up timer description below), causing the internal chip reset to remain asserted until th e external reset is de-asserted, the oscillator is running, a fixed number of clocks have passed, and the on-chip flash controller has completed its initialization. when the internal reset is removed, the proc essor begins executing at address 0, which is the reset vector. at that point, all of the processor and peripheral registers have been initialized to prede termined values. the wake-up timer ensures that the oscillator and other anal og functions required for chip operation are fully functional before the proce ssor is allowed to exec ute instructions. this is important at power on, all types of reset, and whenever any of the aforementioned functions are turned off for any reason. since the oscillator and other functions are turned off during power-down mode, any wake-up of the processor from power-down mode makes use of the wake-up timer. the wake-up timer monito rs the crystal oscillator as the me ans of checking whether it is safe to begin code execution. when power is applied to the chip, or some event caused the chip to exit powe r-down mode, some time is required for the oscillator to produce a signal of sufficient amplitude to drive the clock logic. the amount of time depends on many factors, including the rate of v dd ramp (in the case of power on), the type of crystal and its electrical characteristics (if a quartz cr ystal is used), as well as any other external circuitry (e.g. capacitors), and the characteristics of the oscilla tor itself under the existing ambient conditions. 6.18.4 code security (code read protection - crp) this feature of the lpc2109/2119/2129 allows the user to enable different levels of security in the system so that access to the on-chip flash and use of the jtag and isp can be restricted. when needed, crp is invoked by programming a specific pattern into a dedicated flash location. iap commands are not affected by the crp. there are three levels of the code read protection.
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 22 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers crp1 disables access to chip via the jtag and allows partial flash update (excluding flash sector 0) using a limited set of the is p commands. this mode is useful when crp is required and flash field updates are needed but all sectors can not be erased. crp2 disables access to chip via the jtag and only allows full flash erase and update using a reduced set of the isp commands. running an application with level crp3 selected fully disa bles any access to chip via the jtag pins and the isp. this mode effectively disables isp override using p0[14] pin, too. it is up to the user?s application to provide (if needed) flash update mechanism using iap calls or call reinvoke isp command to enable flash update via uart0. remark: devices without the suffix /00 or /01 have only a security level equivalent to crp2 available. 6.18.5 external interrupt inputs the lpc2109/2119/2129 include up to nine ed ge or level sensitive external interrupt inputs as selectable pin functions. when the pins are combined, external events can be processed as four independent interrupt si gnals. the external interrupt inputs can optionally be used to wake up the processor from power-down mode. 6.18.6 memory mapping control the memory mapping control alters the mapp ing of the interrupt vectors that appear beginning at address 0x0000 0000. vectors may be mapped to the bottom of the on-chip flash memory, or to the on-chip sram. this allows code running in different memory spaces to have control of the interrupts. 6.18.7 power control the lpc2109/2119/2129 support two reduced power modes: idle mode and power-down mode. in idle mode, execution of instructions is suspended until either a reset or interrupt occurs. peripheral functions continue opera tion during idle mode and may generate interrupts to cause the processor to resume execution. idle mode eliminates power used by the processor itself, memory systems and related controllers, and internal buses. in power-down mode, the oscillator is shut down and the chip receives no internal clocks. the processor state and registers, peripheral registers, and internal sram values are preserved throughout power-down mode and th e logic levels of chip output pins remain static. the power-down mode can be terminated and normal operation resumed by either a reset or certain specific in terrupts that are able to function without clocks. since all dynamic operation of the chip is suspended, power-down mode reduces chip power consumption to nearly zero. a power control for peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings. caution if level three code read protection (crp3) is selected, no future factory testing can be performed on the device.
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 23 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers 6.18.8 apb the apb divider determines the relationship between the proc essor clock (cclk) and the clock used by peripheral devices (pclk). the apb divider serv es two purposes. the first is to provide peripher als with the desired pclk via apb so that they can operate at the speed chosen for the arm proc essor. in order to achiev e this, the apb may be slowed down to 1 2 to 1 4 of the processor clock rate. becaus e the apb must work properly at power-up (and its timing cannot be altered if it does not work since the apb divider control registers reside on the apb), the default condition at re set is for the apb to run at 1 4 of the processor clock rate. the sec ond purpose of the apb divider is to allow power savings when an application does not require any peripherals to run at the full processor rate. because the apb divider is connected to the pl l output, the pll remain s active (if it was running) during idle mode. 6.19 emulation and debugging the lpc2109/2119/2129 support emulation and debugging via a jtag serial port. a trace port allows tracing program execution. de bugging and trace functions are multiplexed only with gpios on port 1. this means th at all communication, timer and interface peripherals residing on port 0 are availabl e during the development and debugging phase as they are when the application is run in the embedded system itself. 6.19.1 embeddedice standard arm embeddedice logic provides on-chip debug support. the debugging of the target system requires a host computer running the debugger software and an embeddedice protocol convertor. embeddedice protocol convertor converts the remote debug protocol commands to the jtag data needed to access the arm core. the arm core has a debug communication channel function built-in. the debug communication channel allows a program running on the target to communicate with the host debugger or another separate host without stopping the program flow or even entering the debug state. the debug communication channel is accessed as a co-processor 14 by the program running on the arm7tdmi-s core. the debug communication channel allows the jtag port to be used for sending and receiving data without affecting the normal program flow. the debug communication channel data and control registers are mapped in to addresses in the embeddedice logic. the jtag clock (tck) must be slower than 1 6 of the cpu clock (cclk) for the jtag interface to operate. 6.19.2 embedded trace macrocell since the lpc2109/2119/2129 have significant amounts of on-chip memory, it is not possible to determine how the processor core is operating simply by observing the external pins. the etm provides real-t ime trace capability for deeply embedded processor cores. it outputs information about processor ex ecution to the trace port. the etm is connected directly to the arm core and not to the main amba system bus. it compresses the trace information and exports it through a narrow trace port. an external trace port analyzer must capture the trace information under software debugger control. instruction trace (or pc trace) shows the flow of execution of the processor and provides a list of all the instructions that were executed. instruction trace is significantly compressed by only broadcasting branch addresses as well as a set of status signals that indicate the
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 24 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers pipeline status on a cycle by cycle basis. trace information generation can be controlled by selecting the trigger resource. trigger resources include address comparators, counters and sequencers. since trace information is compressed the software debugger requires a static image of the code being exec uted. self-modifying code can not be traced because of this restriction. 6.19.3 realmonitor realmonitor is a configurable software module, developed by arm inc., which enables real time debug. it is a lightweight debug monitor that runs in the background while users debug their foreground application. it communicates with the host using the dcc (debug communications channel), which is present in the embeddedice logic. the lpc2109/2119/2129 contain a specific co nfiguration of realmonitor software programmed into the on-chip flash memory.
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 25 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers 7. limiting values [1] the following applies to table 5 : a) this product includes circuitry specif ically designed for the protection of its in ternal devices from the damaging effects of excessive static charge. nonetheless, it is sugges ted that conventional precautions be tak en to avoid applying greater than the rated maximum. b) parameters are valid over operating te mperature range unless otherwise specifi ed. all voltages are with respect to v ss unless otherwise noted. [2] internal rail. [3] external rail. [4] including voltage on outputs in 3-state mode. [5] only valid when the v dd(3v3) supply voltage is present. [6] not to exceed 4.6 v. [7] per supply pin. [8] the peak current is limited to 25 times the corresponding maximum current. [9] per ground pin. [10] dependent on package type. [11] human body model: equivalent to dischar ging a 100 pf capacitor through a 1.5 k ? series resistor. table 5. limiting values in accordance with the absolute ma ximum rating system (iec 60134). [1] symbol parameter conditions min max unit v dd(1v8) supply voltage (1.8 v) [2] ? 0.5 +2.5 v v dd(3v3) supply voltage (3.3 v) [3] ? 0.5 +3.6 v v dda(3v3) analog supply voltage (3.3 v) ? 0.5 +4.6 v v ia analog input voltage ? 0.5 +5.1 v v i input voltage 5 v tolerant i/o pins [4] [5] ? 0.5 +6.0 v other i/o pins [4] [6] ? 0.5 v dd(3v3) + 0.5 v i dd supply current [7] [8] - 100 ma i ss ground current [8] [9] - 100 ma t j junction temperature - 150 ?c t stg storage temperature [10] ? 65 +150 ?c p tot(pack) total power dissipation (per package) based on package heat transfer, not device power consumption -1.5 w v esd electrostatic discharge voltage human body model; all pins [11] ? 2000 +2000 v
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 26 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers 8. static characteristics table 6. static characteristics t amb = ? 40 ? c to +85 ? c for industrial applications, unless otherwise specified. symbol parameter conditions min typ [1] max unit v dd(1v8) supply voltage (1.8 v) [2] 1.65 1.8 1.95 v v dd(3v3) supply voltage (3.3 v) [3] 3.0 3.3 3.6 v v dda(3v3) analog supply voltage (3.3 v) 2.5 3.3 3.6 v standard port pins, reset , rtck i il low-level input current v i = 0 v; no pull-up - - 3 ? a i ih high-level input current v i =v dd(3v3) ; no pull-down - - 3 ? a i oz off-state output current v o =0v; v o =v dd(3v3) ; no pull-up/down --3 ? a i latch i/o latch-up current ? (0.5v dd(3v3) ) < v i < (1.5v dd(3v3) ); t j < 125 ?c 100 - - ma v i input voltage [4] [5] [6] 0-5 . 5v v o output voltage output active 0 - v dd(3v3) v v ih high-level input voltage 2.0 - - v v il low-level input voltage - - 0.8 v v hys hysteresis voltage 0.4 - - v v oh high-level output voltage i oh = ? 4 ma [7] v dd(3v3) ? 0.4 - - v v ol low-level output voltage i ol =4 ma [7] --0 . 4v i oh high-level output current v oh =v dd(3v3) ? 0.4 v [7] ? 4- -ma i ol low-level output current v ol =0.4v [7] 4--m a i ohs high-level short-circuit output current v oh =0v [8] -- ? 45 ma i ols low-level short-circuit output current v ol =v dd(3v3) [8] --5 0m a i pd pull-down current v i =5v [9] 10 50 150 ? a i pu pull-up current v i =0v [10] ? 15 ? 50 ? 85 ? a v dd(3v3) < v i < 5 v [9] 000 ? a
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 27 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers power consumption lpc2109/00, lpc21 19, lpc2119/00, lpc2129, lpc2129/00 i dd(act) active mode supply current v dd(1v8) =1.8v; cclk = 60 mhz; t amb =25 ? c; code while(1){} executed from flash; all peripherals enabled via pconp [11] register but not configured to run -60-ma i dd(pd) power-down mode supply current v dd(1v8) =1.8v; t amb =25 ?c -10- ? a v dd(1v8) =1.8v; t amb =85 ?c - 110 500 ? a power consumption lpc2109/01, lpc2119/01, lpc2129/01 i dd(act) active mode supply current v dd(1v8) =1.8v; cclk = 60 mhz; t amb =25 ? c; code while(1){} executed from flash; all peripherals enabled via pconp [11] register but not configured to run -4 1 . 5-m a i dd(idle) idle mode supply current v dd(1v8) =1.8v; cclk = 60 mhz; t amb =25 ?c; executed from flash; all peripherals enabled via pconp [11] register but not configured to run -9-ma i dd(pd) power-down mode supply current v dd(1v8) =1.8v; t amb =25 ?c -10- ? a v dd(1v8) =1.8v; t amb =85 ?c - 110 500 ? a i 2 c-bus pins v ih high-level input voltage 0.7v dd(3v3) --v v il low-level input voltage - - 0.3v dd(3v3) v v hys hysteresis voltage - 0.05v dd(3v3) -v v ol low-level output voltage i ols =3 ma [7] --0 . 4v i li input leakage current v i =v dd(3v3) [12] -24 ? a v i =5v - 10 22 ? a table 6. static characteristics ?continued t amb = ? ? ? symbol parameter conditions min typ [1] max unit
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 28 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers [1] typical ratings are not guaranteed. the va lues listed are at room temperature (25 ? c), nominal supply voltages. [2] internal rail. [3] external rail. [4] including voltage on outputs in 3-state mode. [5] v dd(3v3) supply voltages must be present. [6] 3-state outputs go into 3-state mode when v dd(3v3) is grounded. [7] accounts for 100 mv voltage drop in all supply lines. [8] only allowed for a short time period. [9] minimum condition for v i = 4.5 v, maximum condition for v i =5.5v. [10] applies to p1[25:16]. [11] see lpc2119/2129/2194/2292/2294 user manual . [12] to v ss . oscillator pins v i(xtal1) input voltage on pin xtal1 0-1.8v v o(xtal2) output voltage on pin xtal2 0-1.8v table 6. static characteristics ?continued t amb = ? 40 ? c to +85 ? c for industrial applications, unless otherwise specified. symbol parameter conditions min typ [1] max unit
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 29 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers [1] conditions: v ssa =0v, v dda =3.3v. [2] the adc is monotonic, there are no missing codes. [3] the differential linearity error (e d ) is the difference between the actual step width and the ideal step width. see figure 4 . [4] the integral non-linearity (e l(adj) ) is the peak difference between the center of the st eps of the actual and the ideal transfer curve after appropriate adjustment of gain and offset errors. see figure 4 . [5] the offset error (e o ) is the absolute difference between the straight line which fits the actual cu rve and the straight line which fits the ideal curve. see figure 4 . [6] the gain error (e g ) is the relative difference in percent between the straight line fitting the actual transfe r curve after removing offset error, and the straight line which fits the ideal transfer curve. see figure 4 . [7] the absolute voltage error (e t ) is the maximum difference between the center of the steps of the actual transfer curve of the non-calibrated adc and the ideal transfer curve. see figure 4 . table 7. adc static characteristics v dda = 2.5 v to 3.6 v unless otherwise specified; t amb = ? 40 ? c to +85 ? c unless otherwise spec ified. adc frequency 4.5 mhz. symbol parameter conditions min typ max unit v ia analog input voltage 0 - v dda v c ia analog input capacitance --1pf e d differential linearity error [1] [2] [3] -- ? 1lsb e l(adj) integral non-linearity [1] [4] -- ? 2lsb e o offset error [1] [5] -- ? 3lsb e g gain error [1] [6] -- ? 0.5 % e t absolute error [1] [7] -- ? 4lsb
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 30 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers (1) example of an actual transfer curve. (2) the ideal transfer curve. (3) differential linearity error (e d ). (4) integral non-linearity (e l(adj) ). (5) center of a step of the actual transfer curve. fig 4. adc characteristics 002aaa668 1023 1022 1021 1020 1019 (2) (1) 1024 1018 1019 1020 1021 1022 1023 7 123456 7 6 5 4 3 2 1 0 1018 (5) (4) (3) 1 lsb (ideal) code out v dda ? v ssa 1024 offset error e o gain error e g offset error e o v ia (lsb ideal ) 1 lsb =
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 31 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers 8.1 power consumption measureme nts for lpc2109/01, lpc2119/01, lpc2129/01 devices the power consumption measurements represent typical values for the given conditions. the peripherals were enabled through the pconp register, but for these measurements, the peripherals were not configured to run. peripherals were disabled through the pconp register. refer to the lpc2119/2129/2194/2292/2294 user manual for a description of the pconp register. test conditions: active mode entered exec uting code from on-chip flash; pclk = cclk 4 ; t amb =25 ? c; core voltage 1.8 v. fig 5. typical lpc2109/01 i dd(act) measured at different frequencies 002aad127 25 15 35 45 i dd(act) (ma) 5 frequency (mhz) 12 60 44 28 20 52 36 all peripherals enabled all peripherals disabled test conditions: active mode entered exec uting code from on-chip flash; pclk = cclk 4 ; t amb = 25 ? c; core voltage 1.8 v; all peripherals enabled. fig 6. typical lpc2109/01 i dd(act) measured at different voltages 002aad128 25 15 35 45 i dd(act) (ma) 5 voltage (v) 1.65 1.95 1.85 1.75 1.70 1.90 1.80 60 mhz 48 mhz 12 mhz
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 32 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers test conditions: idle mode entered executing code from on-chip flash; pclk = cclk 4 ; t amb = 25 ? c; core voltage 1.8 v. fig 7. typical lpc2109/01 i dd(idle) measured at different frequencies 002aad129 4 6 2 8 10 i dd(idle) (ma) 0 frequency (mhz) 12 60 44 28 20 52 36 all peripherals enabled all peripherals disabled test conditions: idle mode entered executing code from on-chip flash; pclk = cclk 4 ; t amb =25 ? c; core voltage 1.8 v; all peripherals enabled. fig 8. typical lpc2109/01 i dd(idle) measured at different voltages 002aad130 5.0 2.5 7.5 10 i dd(idle) (ma) 0 voltage (v) 1.65 1.95 1.85 1.75 1.70 1.90 1.80 60 mhz 48 mhz 12 mhz
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 33 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers test conditions: active mode entered exec uting code from on-chip flash; pclk = cclk 4 ; t amb =25 ? c; core voltage 1.8 v. fig 9. typical lpc2119/01 and lpc2129/01 i dd(act) measured at different frequencies 002aad131 25 15 35 45 i dd(act) (ma) 5 frequency (mhz) 12 60 44 28 20 52 36 all peripherals enabled all peripherals disabled test conditions: active mode entered exec uting code from on-chip flash; pclk = cclk 4 ; t amb = 25 ? c; core voltage 1.8 v; all peripherals enabled. fig 10. typical lpc2119/01 and lpc2129/01 i dd(act) measured at different voltages 002aad132 20 30 10 40 50 i dd(act) (ma) 0 voltage (v) 1.65 1.95 1.85 1.75 1.70 1.90 1.80 60 mhz 48 mhz 12 mhz
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 34 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers test conditions: idle mode entered executing code from on-chip flash; pclk = cclk 4 ; t amb = 25 ? c; core voltage 1.8 v. fig 11. typical lpc2119/01 and lpc2129/01 i dd(idle) measured at different frequencies 002aad133 4 6 2 8 10 i dd(idle) (ma) 0 frequency (mhz) 12 60 44 28 20 52 36 all peripherals enabled all peripherals disabled test conditions: idle mode entered executing code from on-chip flash; pclk = cclk 4 ; t amb =25 ? c; core voltage 1.8 v; all peripherals enabled. fig 12. typical lpc2119/01 and lpc2129/01 i dd(idle) measured at different voltages 002aad134 4 6 2 8 10 i dd(idle) (ma) 0 voltage (v) 1.65 1.95 1.85 1.75 1.70 1.90 1.80 60 mhz 48 mhz 12 mhz
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 35 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers test conditions: active mode entered exec uting code from on-chip flash; pclk = cclk 4 ; te m p = 2 5 ? c; core voltage 1.8 v; all peripherals disabled. fig 13. typical lpc2109/01, lpc2119/01, and lpc2129/01 i dd(act) measured at different voltages 002aad135 25 15 35 45 i dd(act) (ma) 5 voltage (v) 1.65 1.95 1.85 1.75 1.70 1.90 1.80 60 mhz 48 mhz 12 mhz test conditions: idle mode entered executing code from on-chip flash; pclk = cclk 4 ; te m p = 2 5 ? c; core voltage 1.8 v; all peripherals disabled. fig 14. typical lpc2109/01, lpc2119/01, and lpc2129/01 i dd(idle) measured at different voltages 002aad136 4 2 6 8 i dd(idle) (ma) 0 voltage (v) 1.65 1.95 1.85 1.75 1.70 1.90 1.80 60 mhz 48 mhz 12 mhz
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 36 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers test conditions: active mode entered exec uting code from on-chip flash; pclk = cclk 4 ; core voltage 1.8 v; all peripherals disabled. fig 15. typical lpc2109/01, lpc2119/01, and lpc2129/01 i dd(act) measured at different temperatures 002aad137 25 15 35 45 i dd(act) (ma) 5 temperature ( c) ?40 85 60 10 35 ?15 60 mhz 48 mhz 12 mhz test conditions: idle mode entered executing code from on-chip flash; pclk = cclk 4 ; core voltage 1.8 v; all peripherals disabled. fig 16. typical lpc2109/01, lpc2119/01, and lpc2129/01 i dd(idle) measured at different temperatures 002aad138 3 4 2 5 6 i dd(idle) (ma) 1 temperature ( c) ?40 85 60 10 35 ?15 60 mhz 48 mhz 12 mhz
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 37 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers test conditions: power-down mode entered executing code from on-chip flash. fig 17. typical lpc2109/01, lpc2119/01, and lpc2129/01 core power-down current i dd(pd) measured at different temperatures 002aad139 80 120 40 160 200 i dd(pd) (a) 0 temperature ( c) ?40 85 60 10 35 ?15 1.95 v 1.8 v 1.65 v table 8. typical lpc2109/01 peripheral power consumption in active mode core voltage 1.8 v; t amb =25 ? c; all measurements in ? a; pclk = cclk 4 . peripheral cclk = 12 mhz cclk = 48 mhz cclk = 60 mhz timer0 43 141 184 timer1 46 150 180 uart0 98 320 398 uart1 103 351 421 pwm0 103 341 407 i 2 c-bus 9 37 53 spi0/1 6 27 29 r t c1 65 57 8 adc 33 128 167 can1 230 764 914
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 38 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers table 9. typical lpc2119/01 an d lpc2129/01 peripheral power consumption in active mode core voltage 1.8 v; t amb =25 ? c; all measurements in ? a; pclk = cclk 4 . peripheral cclk = 12 mhz cclk = 48 mhz cclk = 60 mhz timer0 43 141 184 timer1 46 150 180 uart0 98 320 398 uart1 103 351 421 pwm0 103 341 407 i 2 c-bus 9 37 53 spi0/1 6 27 29 r t c1 65 57 8 adc 33 128 167 can1/2 229 771 914
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 39 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers 9. dynamic characteristics [1] parameters are valid over operating tem perature range unless otherwise specified. [2] bus capacitance c b in pf, from 10 pf to 400 pf. table 10. dynamic characteristics t amb = ? 40 ? c to +85 ? c for industrial applications; v dd(1v8) , v dd(3v3) over specified ranges. [1] symbol parameter conditions min typ max unit external clock f osc oscillator frequency supplied by an external oscillator (signal generator) 1-50mhz external clock frequency supplied by an external crystal oscillator 1-30mhz external clock frequency if on-chip pll is used 10 - 25 mhz external clock frequency if on-chip bootloader is used for initial code download 10 - 25 mhz t cy(clk) clock cycle time 20 - 1000 ns t chcx clock high time t cy(clk) ? 0.4--ns t clcx clock low time t cy(clk) ? 0.4--ns t clch clock rise time - - 5 ns t chcl clock fall time - - 5 ns port pins (excep t p0[2] and p0[3]) t r rise time - 10 - ns t f fall time - 10 - ns i 2 c-bus pins (p0[2] and p0[3]) t f fall time v ih to v il [2] 20 + 0.1 ? c b --ns
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 40 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers 9.1 timing fig 18. external clock timing (wit h an amplitude of at least v i(rms) = 200 mv) t chcl t clcx t chcx t cy(clk) t clch 002aaa907
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 41 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers 10. package outline fig 19. package outline sot314-2 (lqfp64) unit a max. a 1 a 2 a 3 b p ce (1) eh e ll p z ywv references outline version european projection issue date iec jedec jeita mm 1.6 0.20 0.05 1.45 1.35 0.25 0.27 0.17 0.18 0.12 10.1 9.9 0.5 12.15 11.85 1.45 1.05 7 0 o o 0.12 0.1 1 0.2 dimensions (mm are the original dimensions) note 1. plastic or metal protrusions of 0.25 mm maximum per side are not included. 0.75 0.45 sot314-2 ms-026 136e10 00-01-19 03-02-25 d (1) (1)(1) 10.1 9.9 h d 12.15 11.85 e z 1.45 1.05 d b p e e a 1 a l p detail x l (a ) 3 b 16 c d h b p e h a 2 v m b d z d a z e e v m a x 1 64 49 48 33 32 17 y pin 1 index w m w m 0 2.5 5 mm scale lqfp64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm sot314-2
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 42 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers 11. abbreviations table 11. abbreviations acronym description adc analog-to-digital converter amba advanced microcontroller bus architecture apb advanced peripheral bus can controller area network cpu central processing unit dcc debug communications channel fifo first in, first out gpio general purpose input/output i/o input/output pll phase-locked loop pwm pulse width modulator ram random access memory spi serial peripheral interface sram static random access memory ssi synchronous serial interface ssp synchronous serial port ttl transistor-transistor logic uart universal asynchronous receiver/transmitter
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 43 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers 12. revision history table 12. revision history document id release date data sheet status change notice supersedes lpc2109_2119_2129 v.7 20110614 product data sheet 201004021f lpc2109_2119_2129 v.6 modifications: ? table 6 ? static characteristics ? ; changed /01 power-down mode supply current (i dd(pd) ) from 180 ? a to 500 ? a for industrial temperature range. ? table 6 ? static characteristics ? ; moved v hys voltage from typical to minimum. ? table 6 ? static characteristics ? ; changed i 2 c pad hysteresis from 0.5v dd(3v3) to 0.05v dd(3v3) . lpc2109_2119_2129 v.6 20071210 product data sheet - lpc2109_2119_2129 v.5 modifications: ? type number lpc2109fbd64/01 has been added. ? type number LPC2119FBD64/01 has been added. ? type number lpc2129fbd64/01 has been added. ? details introduced with /01 devices on new per ipherals/features (fast i/o ports, ssp, crp) and enhancements to existing ones (uart0/1, timers, adc, and spi) have been added. ? power measurements for lpc2109/2119/2129/01 devices have been added. ? description of jtag pin tck has been updated. lpc2109_2119_2129 v.5 20070627 product data sheet - lpc2119_2129 v.4 lpc2119_2129 v.4 20060714 product data sheet - lpc2119_2129 v.3 lpc2119_2129 v.3 20041222 product data - lpc2119_2129 v.2 lpc2119_2129 v.2 20040202 preliminary data - lpc2119_2129 v.1 lpc2119_2129 v.1 20031118 preliminary data - -
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 44 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers 13. legal information 13.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 13.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 13.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from national authorities. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
lpc2109_2119_2129 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved . product data sheet rev. 7 ? 14 june 2011 45 of 46 nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 13.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. i 2 c-bus ? logo is a trademark of nxp b.v. 14. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors lpc2109/2119/2129 single-chip 16/32-bit microcontrollers ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 14 june 2011 document identifier: lpc2109_2119_2129 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 15. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 2.1 key features brought by lpc2109/2119/2129/01 devices. . . . . . . . . . . . 1 2.2 key features common for all devices . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 3.1 ordering options . . . . . . . . . . . . . . . . . . . . . . . . 3 4 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 functional description . . . . . . . . . . . . . . . . . . 10 6.1 architectural overview . . . . . . . . . . . . . . . . . . 10 6.2 on-chip flash program memo ry . . . . . . . . . . . 10 6.3 on-chip sram . . . . . . . . . . . . . . . . . . . . . . . . 11 6.4 memory map. . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.5 interrupt controller . . . . . . . . . . . . . . . . . . . . . 12 6.5.1 interrupt sources. . . . . . . . . . . . . . . . . . . . . . . 13 6.6 pin connect block . . . . . . . . . . . . . . . . . . . . . . 14 6.7 general purpose parallel i/o (gpio) and fast i/o . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.7.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 6.7.2 features added with the fast gpio set of registers available on lpc2109/2119/2129/01 only . . . . . . . . . . . . . 14 6.8 10-bit adc . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.8.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.8.2 adc features available in lpc2109/2119/2129/01 only . . . . . . . . . . . . . 15 6.9 can controllers and acceptance filter . . . . . . 15 6.9.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.10 uarts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.10.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 6.10.2 uart features available in lpc2109/2119/2129/01 only . . . . . . . . . . . . . 16 6.11 i 2 c-bus serial i/o controller . . . . . . . . . . . . . . 16 6.11.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6.12 spi serial i/o controller. . . . . . . . . . . . . . . . . . 17 6.12.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.12.2 features available in lpc2109/2119/2129/01 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.13 ssp controller (lpc2 109/2119/2129/ 01 only) 17 6.13.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.14 general purpose timers . . . . . . . . . . . . . . . . . 17 6.14.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.14.2 features available in lpc2109/2119/2129/01 only . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.15 watchdog timer . . . . . . . . . . . . . . . . . . . . . . . 18 6.15.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.16 real-time clock . . . . . . . . . . . . . . . . . . . . . . . 19 6.16.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.17 pulse width modulator . . . . . . . . . . . . . . . . . . 19 6.17.1 features. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.18 system control . . . . . . . . . . . . . . . . . . . . . . . . 20 6.18.1 crystal oscillator. . . . . . . . . . . . . . . . . . . . . . . 20 6.18.2 pll. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.18.3 reset and wake-up timer . . . . . . . . . . . . . . . . 21 6.18.4 code security (code read protection - crp) 21 6.18.5 external interr upt inputs . . . . . . . . . . . . . . . . . 22 6.18.6 memory mapping control . . . . . . . . . . . . . . . . 22 6.18.7 power control . . . . . . . . . . . . . . . . . . . . . . . . . 22 6.18.8 apb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6.19 emulation and debugging . . . . . . . . . . . . . . . 23 6.19.1 embeddedice . . . . . . . . . . . . . . . . . . . . . . . . 23 6.19.2 embedded trace macrocell . . . . . . . . . . . . . . 23 6.19.3 realmonitor . . . . . . . . . . . . . . . . . . . . . . . . . . 24 7 limiting values . . . . . . . . . . . . . . . . . . . . . . . . 25 8 static characteristics . . . . . . . . . . . . . . . . . . . 26 8.1 power consumption measurements for lpc2109/01, lpc2119/01, lpc2129/01 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 9 dynamic characteristics. . . . . . . . . . . . . . . . . 39 9.1 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 10 package outline. . . . . . . . . . . . . . . . . . . . . . . . 41 11 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . 42 12 revision history . . . . . . . . . . . . . . . . . . . . . . . 43 13 legal information . . . . . . . . . . . . . . . . . . . . . . 44 13.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 44 13.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 13.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 44 13.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 45 14 contact information . . . . . . . . . . . . . . . . . . . . 45 15 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

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